Size-depth-alternation tradeoffs for circuits

A Boolean circuit is a directed acyclic graph with some designated input gates of fan-in zero and one designated output gate of fan-out zero in which all non-input nodes are labeled with or, and, or not. All or and and gates have fan-in two, and all not gates fan-in one. We assume that the gates of a Boolean circuit are arranged in layers; each layer consists of gates whose inputs come only from the previous layer and whose outputs feed only the following layer. The depth, or layer number, of a gate is the length of the shortest path from any input node to the gate; the depth of the circuit is the depth of the output gate. The input gates are in the first layer and the output gate is in the last layer. We assume that the first layer after the input layer consists of only not gates, and no not gates appear anywhere else. A configuration of a Boolean circuit is a triple (1, i, w), where n is the number of inputs, i is the layer number (in binary), and w is the contents of the wires after layer i (given as a single binary string). If C is a circuit, configuration (1, i, u) yields configuration (1, i+ 1, v) if layer i+ 1 of the circuit produces output bits v when provided with input bits w. Configuration (1, i, u) yields configuration (1, i+ t, v) within t steps of there is a sequence of binary strings w0, . . . , wt such that • u = w0 • (1, i+ k,wk) yields (1, i+ k + 1, wk+1) for all k ∈ {0, . . . , t− 1}